
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Retardo is
    Port ( CLK : in  STD_LOGIC;
           CLK_out : out  STD_LOGIC := '0'
			 );
end Retardo;

architecture Arq_Retardo of Retardo is

--signal contador: std_logic_vector(9 DOWNTO 0):="0000000000";
signal counter: integer range 0 to 20_000_000:=0;

begin

process(clk)
	begin
		if rising_edge(clk) then
			counter <=counter+1;
			CLK_out<='0';
			if counter >=1_125_000 then --3_125_000
				counter<=0;
				CLK_out<='1';
			end if;
		end if;
	end process;

end Arq_Retardo;

